The necessity of supporting information processing needs have made memory devices and systems more and more complex and diversified. Moreover, it has become highly advantageous to execute read and write operations simultaneously. This has led to the advent of dual port memory, which provides two access ports (e.g., left and right ports) that can access a common memory array. Dual port memory allows one port to be used for a write operation even when the other port is being used for a read operation.
One type of basic storage memory is static random access memory (SRAM). The advantage of SRAM is that it does not require additional refresh, as it employs latch type cells. In additional, SRAM can retain its memory state without refreshing, as long as power is supplied to the cells.
Conventionally, one unit memory cell of a single port SRAM device is composed of six transistors, i.e., two load transistors, two drive transistors and two active transistors, to perform read and write operations sequentially. In contrast, a dual port SRAM device includes eight transistors, i.e., two load transistors, two drive transistors and four active transistors to perform the read and write operations in a dual mode.
FIG. 1 illustrates a circuit diagram 100 of a conventional single unit of dual port SRAM cell. It includes two load transistors 102 and 104, two drive transistors 106 and 108 and four active transistors 110, 112, 114 and 116. The two load transistors 102 and 104 and the two drive transistors 106 and 108 are individually connected to form two invertors. The two invertors are cross coupled so as to form a latch for storing data. The drain of the active transistor 110 is connected to a read bit line RBL, with the source is connected to the latch output node and the gate is connected to a read word line RWL. The drain of the active transistor 112 is connected to a complementary read bit line RBLB, the source is connected to the latch output node and the gate is connected to the read word line RWL. The drain of the active transistor 114 is connected to a write bit line WBL, the source is connected to the latch output node and the gate is connected to a write word line WWL. The drain of the active transistor 116 is connected to a complementary write bit line WBLB, the source is connected to the latch output node and the gate is connected to the write word line WWL.
Thus, there are two different ports through which read and write operations can be performed simultaneously. To read a particular data, a word line signal for read operation is enabled as logic low ‘L’. As a result, the two active transistors 110 and 112 are turned on and the data stored at the latch is read through the read bit line RBL and the complementary bit line RBLB. In the case of write operation, a word line signal for a write operation is enabled as logic high ‘H’. The transistors 114 and 116 are turned on and the data loaded on the bit line and the complementary bit line is stored at the latch.
However, as seen from FIG. 1, there is an interaction between the read and write operations if both the read and the write word lines are on simultaneously. This results in crosstalk and brings about a characteristic drop in the dual port SRAM cell. This drawback can be minimized by tuning write and read pass transistors so as to benefit one operation more at the expense of other, while still maintaining a somewhat robust configuration. However, this defeats the very purpose of dual port SRAM, i.e., the ability to perform simultaneously the read and write operations. Moreover, to reduce static leakage of the cell, all transistors are doped with high Vt layer in sub nanometer technologies (CMOS 90 nm onwards). This results in further degradation of speed as pass gates and latch NMOS transistors come in series both with high Vt implant.
To overcome the above identified problems, another circuit 200 was designed, in which the gate of the active transistors 202 and 204 are connected to the output of the latch and a source of the transistors are connected to a read enable control signal RE as illustrated in FIG. 2. In this way, the interaction between the read and write operations are eliminated. However, this method presents another problem, in that the read enable RE has to drive all the bit lines and that requires a very wide metal line for RE (to eliminate risk of electro migration) as illustrated in FIG. 3. As the size of the metal line is very wide, the metal line will not fit into a memory cell's height. Also, due to huge current flowing in RE line, there is a rise in the voltage level of this signal which severely impacts performance of the last column (as the rise will be the maximum in the last column).
However, if the memory using the above scheme is self-timed, leakage on bit lines of unselected rows can be eliminated. Read pass transistors then need to be made as large as possible considering area constraint, and write flip time as capacitance on internal nodes increases. In addition, the size of a pull down NMOS driving the RE to ground needs to be very big, which causes a big static power loss (as this pull down will have Vds=Vdd available).
In order to overcome the problem of having very wide metal line for RE, another circuit 400 can be used, in which the sources of the active transistors 402 and 404 are connected to the ground through a pull down transistor 406 as illustrated in FIG. 4. The sources of the active transistors 402, 404 are connected to the ground through the pull down transistor 406. The pull down transistor 406 will pull down the voltage of the signal. This method can be used for memories not employing self-time. However, this cell will be asymmetric with respect to center (where PMOS transistors will be made in N-well). Also, it suffers from dynamic leakage on bit lines. A larger size of the pass gate, will result in larger dynamic leakage. The magnitude of the static leakage is less as compared to the methods discussed above. In this case area requirement in memory cell is also higher which is somewhat compensated due to lesser decoder area than previous schemes. However, the overall area will be higher as there is a discrete pull down in every cell.
FIG. 5 illustrates a method to obtain a high performance by using a logic implant in a SRAM. Four NMOS transistors 502, 504, 506 and 508 are connected to a SRAM implant to perform a read operation. The drain of the NMOS transistor 502 is connected to the read bit line RBL, the source of NMOS transistor 502 is connected to the drain of NMOS transistor 504. The gate of NMOS transistor 502 is connected to the read word line RWL. The gate of the NMOS transistor 504 is connected to the output of the latch and the source is at ground voltage. Similar connection is made for NMOS transistors 506 and 508. The logic implant performs the read operation. Thus, this cell does not suffer from asymmetric structure. However, as large numbers of gates are used in the memory cell itself, a large area is required, and dynamic as well as the static leakage of this cell will be even greater than the previous methods. If the threshold voltages of memory cell components are increased, the static power can be reduced. However, this will degrade the cell's performance drastically.
To improve read performance in the above configuration, only the read pass gates and corresponding pull downs are kept in logic thresholds, unfortunately at the expense of leakage. This needs to be done if the purpose of the cell is to be achieved, i.e., to a give high performance and if the area is not to be increased a lot. However, this structure suffers from risks arising due to mixing of logic and SRAM (relatively high threshold voltage devices) and requires a big area increase to follow normal Design Rules Checking (DRC) to separate logic and SRAM devices. Moreover, there is a reliability risk of repeated mixing of logic (low Vt) implant and SRAM (high Vt) implant.
The prior art discussed above does not overcome the major prevailing problems in the field of dual port SRAM for simultaneous read and write operations. Problems like lower speed due to interactions between read and write ports, a very wide metal line for read enable (RE) signal, static power loss due to big pull down transistor for RE, dynamic and static leakages, asymmetric structure and bigger area, etc., still persists. Thus, there remains a need for a novel SRAM architecture to provide a high speed read operation with reduced leakages.